Chapman Consulting – San Jose, CA
EDA Software Developer, Expert Witness
David C. Chapman
Electronic Design Automation software developer who has written over 1,300,000 lines of code is available for contract work in software development or GDSII/OASIS review as an expert witness.
- 32 years industry experience, over 1,300,000 lines of code written
- has developed algorithms for VLSI EDA tools including logic synthesis, physical design, physical verification, mask tooling, transistor level circuit design, circuit analysis, IP analysis
- understands physical design from transistor level to chip level, algorithms to GDSII/OASIS
- writes efficient, high-quality code
- uses robust testing methodologies for high reliability
- expert at performance optimization (algorithmic enhancements as well as code tuning)
- expert at fixing memory leaks and pointer corruption
- mentor to junior colleagues; unbiased sounding board to everyone
- excellent technical writer
- experienced in C/C++; parallel programming/pthreads; C-shell/AWK; flex/bison; SPICE
- 12 U.S. patents granted
- 1 published article
MSEE, Stanford University, 1991. Concentration in Computer Architecture.
BSCS, California Polytechnic State University, San Luis Obispo, 1984. Concentration in hardware with 3 years of BSEE program. Senior project: designed, constructed, and delivered a microprocessor-controlled data acquisition system.
Chapman Consulting, March 2006 - Present:
Custom software development for the Electronic Design Automation industry: neural networks; optical proximity correction; OASIS reader and writer; Verilog, VHDL, GDS/GDSII, LEF, DEF, Liberty, and SPICE parsers; IP design flow management; research work in transistor level layout synthesis.
Expert witness work: analysis of GDSII/OASIS VLSI design files using industry-standard data viewers, looking for evidence of patent infringement or IP misuse. Case list available upon request.
Consulting has financed my research and development on a tool to perform layout synthesis of standard cells and datapath elements. Four U.S. patents have been issued for this work.
Synplicity, Inc., October 2000 - May 2002, March 2003 - March 2006:
Worked on numerous Quality of Results (QoR) and infrastructure projects for Synplicity's ASIC logic and physical synthesis products including placement-aware timing optimizations; RTL-level timing-driven optimizations; gate-level timing optimizations; critical path analysis.
Chapman Consulting, October 1992 to October 2000; May 2002 to March 2003:
Custom software development for the Electronic Design Automation industry: Mask Tooling work including CMP pattern fill generation; automated circuit delay and power characterization using SPICE; research work in transistor level layout synthesis.
COMPASS Design Automation, July 1984 to June 1991:
Wrote a 2-D interconnect capacitance extractor; prototyped an interconnect resistance extractor; architected a rewrite of the DRC package, leading to a 15x speedup overall; developed a Mask Tooling automation package that became a corporate competitive advantage; co-developed an automated regression test suite manager.
Hired as Software Engineer I; promoted through the years to Staff Software Engineer.
- "Identifying Hierarchical Chip Design Intellectual Property through Digests" - U.S. Patents #8,555,219, #9,122,825
- "Method for Reading Polygon Data into an Integrated Circuit Router" - U.S. Patent #8,352,890
- "Methods and Devices for Independent Evaluation of Cell Integrity, Changes and Origin in Chip Design for Production Workflow" - U.S. Patents #7,685,545, #8,266,571
- "An Approach for Routing an Integrated Circuit" - U.S. Patent #7,506,289
- "An Approach for Routing an Integrated Circuit" - U.S. Patent #7,065,729
- "Method and Apparatus for Design Rule Checking" - U.S. Patent #6,275,971
- "Polygon Representation in an Integrated Circuit Layout" - U.S. Patent #6,128,767
- "A Method of Measuring Energy Consumption in a Circuit Simulator" - U.S. Patent #5,815,416
- "A Method for Labelling Polygons" - U.S. Patent #5,113,451
- "A Method for Making a Reticle Mask" - U.S. Patent #4,849,313
"An Error Manager with Message Text Replacement"; C/C++ Users Journal, April 1995, pp. 23-39